SystemC-WMS: A Wave Mixed Signal Simulator
نویسندگان
چکیده
This paper proposes a methodology for extending SystemC to mixed signal systems, aimed at allowing the reuse of analog models and to the simulation of heterogeneous systems. To this end, a general method for modeling analog modules using wave quantities is suggested, and a new kind of port and channel suitable to let modules communicate via waves have been defined. These entities are plugged directly on top of the standard SystemC kernel, so as to allow a seamless integration with the pre-existing simulation environment, and are designed to permit total interconnection freedom to ease the development of reusable analog libraries.
منابع مشابه
UT Mixed-Signal Simulator
UT Mixed-Signal Simulator is a mixed-signal, mixeddomain, and mixed-language design environment which supports VHDL-AMS 1999, VHDL-2002, Verilog 2001, SystemVerilog 2005 assertions, and SystemC 2005.
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